Experiment: Capacitance Measurement

CV-Meter Module

This experiment uses the C-V meter module to characterise the capacitance of a sensor diode. The measurement is based on the charge-based capacitance measurement (CBCM) technique which is capable of measuring capacitance with a resolution of a few pF. The CBCM method measures an average current which is generated by periodically charging and discharging the capacitance with a constant voltage amplitude. A simplified block diagram of the measurement circuit is shown here:

Simplified diagram of a charge-based capacitance measurement circuit. When switch S1 is closed and S2 is open, the capacitance is charged with a constant voltage amplitude V0 (current path shown in red). When S1 is open and S2 is closed, the capacitance is discharged (current path shown in blue). The average current generated from the periodic charging phases is measured and used to determine the value of the capacitance C.

The switches which control the charging and discharging of the capacitance are steered in a way that only the current from the charging phase is measured (i.e. either S1 or S2 are closed at a time). This leads to an expression for the average current which is proportional to the capacitance, the clock frequency, and the voltage amplitude:

\[I_\text{avg} = C \cdot V_{0} \cdot f_\text{CLK} + I_\text{leak}.\]

The term \(I_\text{leak}\) represents any leakage current of the capacitance, which in particular, for measuring the pn-junction of a sensor diode, cannot be neglected. To suppress this term, the capacitance can be extracted from the slope factor which is derived from the measured current as a function of the clock frequency. The slope factor is given by:

\[S = \frac{dI_\text{avg}}{d(f_\text{CLK})} = C \cdot V_{0}.\]

and therefore

\[C = \frac{S}{V_{0}}.\]

Circuit Implementation

The switches for charing and discharging the capacitance are implemented with a CMOS inverter. The power supply of the inverter is connected via an RC low-pass filter to the voltage source \(V_0\) and the inverter input is connected to a GPIO signal with programmable frequency. The low-pass filter smooths the current transients during the charing phase and thus allows the measurement of the average current. The output of the inverter is connected to the capacitance under test. To characterise the (bias-) voltage dependence of a sensor diode capacitance, the output of the CBCM circuit is ac-coupled. That allows the connection of a bias voltage source to the detector diode. A large series resistor R_bias (1 Meg Ohm) isolates the bias voltage source from the CBCM circuit.

Simplified schematic of the CVM module. The switches are implemented with a CMOS inverter where the NMOS transistor is closed and the PMOS is open during the discharge phase (CLK = high) and the NMOS transistor is open and the PMOS is closed during the charging phase (CLK = low). The full circuit schematic is found here: CVM_1.1.pdf

To apply the voltage \(V_0\) and to measure the current, an SMU-module can be used. The voltage \(V_0\) should be chosen such that the PMOS and NMOS transistors in the CMOS inverter are not switched on at the same time. If \(V_0\) is chosen too high (> 2 times the threshold voltage of a transistor), both transistors will be conducting during an input clock transition which will deteriorate the measurement. If the voltage is chosen too small, the measured current will be small and thus more affected by noise. 1.5 V has been found to be a good compromise for the CBCM measurement.

Exercises

Check the file code/CVM/cvm.py which contains the basic includes, the configuration for implementing a programmable clock with one of the GPIO pins, and code for taking capacitance measurements with the SMU module. Copy it into your work folder and use it as a template for your scripts.

The clock configuration for the CVM module requires calling a C-library which needs root privileges. Therefore, once you navigated to your work directory, you need to start the script with the following command:

sudo -E python cvm.py

Exercise 0 should be solved before coming to the lab.

Exercise 0. Pre-lab questions

1. To measure the average periodic diode charging current, an RC low-pass filter is used. As a secondary consequence, however, the \(R_\text{lpf}\) resistor unforuntately reduces the effective voltage charging the diode capacitance. Modify the equation above to account for this effect. (Hint: If \(I_\text{avg}'\) denotes the actual measured current, express the correction factor \(\frac{I_\text{avg}}{I_\text{avg}'}\).)

2. The ac-coupling capacitor can only be ignored if it is much larger than the capacitance of the diode. If this were not the case, how would you calculate the real capacitance from the measured value?

3. Give the formula of the depletion width of a pn-junction. How does the capacitance of a pn-junction depend on the bias voltage (assuming a plate capacitor configuration)? What expression normalizes a plot of this to a linear linear function?

Exercise 1. Testing of the measurement setup

1. Connect the CVM module to the base board and modify the cvm.py script such that GPIO pin 4 generates a 100 kHz clock signal. Connect an oscilloscope probe to GPIO4 test pin at the Embedded-System-Lab base board and measure the clock frequency.

2. Connect the SMU module to the base board with an flat-ribbon cable and adjust the script such that the SMU module is set to source a voltage of 1.5 V. Measure the voltage with a DVM.

3. First we will characterize the test bench. Connect the output of the SMU module to the LEMO socket on the CVM module labeled “VIN”. (Don’t connect a test capacitor or diode yet). Modify the script so it scans the clock frequency from 100 kHz to 1 MHz in steps of 100 kHz and check that it measures the current at each frequency step.

4. Next, from the of plot the measured current as a function of the clock frequency, compute the offset and slope of this curve (np.polyfit is useful here). Use these to calculate the static leakage current and parasitic capacitance of the testbench circuit.

5. Finally, also connect several test capacitors or BNC cables of various lengths to the socket labeled “SENSOR” and measure their capacitance by similarly extracting the slope factor of the I vs F curve. (Hint: The capacitance of a BNC cable is around 100 pF/m.) Remember to subtract the baseline leakage current first.

Exercise 2. Measure and plot the C-V curve of a sensor diode

This exercise requires the use of an external bias voltage source which can generate up to 30 Volts to deplete the sensor diode. A “KA-3005P” lab power supply that can be controlled via an USB interface will be used for that purpose. The required code is found in the Python file KA3005P.py in the directory code/LabDevices. Use this file and make yourself familiar with the commands to control the power supply. The sensor diode used in this lab is a “BPW 34” silicon photo diode. Here are some parameters form the datasheet:

Parameter	Value
Active area	2.65 mm x 2.65 mm (7.02 mm^2)
Thickness	210 - 300 µm
Reverse breakdown voltage	70 V
Capacitance at zero bias	80 pF
Dark current at 10 V	2 nA

Given the large aspect ration of diode area and thickness one can model the diode capacitance with the equation for a parallel plate capacitor:

\[C = \frac{\epsilon_{0} \cdot \epsilon_{Si} \cdot A}{W}.\]

where \(\epsilon_{0} = 8.854 \cdot 10^-12 \frac{F}{m}\) is the vacuum permittivity, \(\epsilon_{Si} = 11.7\) is the permittivity of silicon, \(A\) is the active area and \(W\) is the width of the depletion zone.

1. Connect the bias supply to the the connector labeled “BIAS” and plug a sensor diode (BPW 34) to the CVM module. Measure the diode capacitance at zero bias (i.e. the bias supply set to 0 Volt output). The measured capacitance should be in the range of 80 to 120 pF. Hint: Make sure that the polarity of the bias voltage is correct, i.e. the inner wire of the coax cable is connected to the positive power supply terminal (the banana plug to BNC adapter is correctly plugged into the power supply outputs ).

2. Now, plot the capacitance of the diode as a function of the bias voltage (C-V curve) in a range from 0 to 30 Volts, with suffient step size to reveal the curve’s shape. Note that each voltage step will require a certain settling time to reach a stable bias potential at the diode.

3. Use the C-V data from the previous measurement and create a plot of the depletion width as a function of the bias voltage. Assume a parallel plate capacitor configuration to calculate the depletion width from the measured capacitance.

4. Is this depletion width from the bias voltage what would you expect for an ideal pn-junction (i.e. abrupt junction and constant doping profile)? Implement the ideal expression for the voltage dependent depletion width of a pn-junction in your code and plot it alongside your measurement. Adjust the parameters of this simulated diode manually to get a similar result range compared to the measurement data. Explain any deviation.

Exercise 3. Extract the doping profile from the C-V measurement

As hinted in the results from the previous exercise, the doping profile of the BAS34 diode is not constant. Actually, this type of diode is a so-called PIN diode, which has a region of very low effective doping density (almost intrinsic) between the p- and n-doped regions (therefore the name “p-i-n”). The doping profile can be calculated from the C-V data using the differential capacitance method. The differential capacitance is defined as:

\[C_{\text{diff}} = \frac{dC}{dV},\]

which is a function of the depletion width \(W\) and the local doping density at this location \(N(W)_{\text{eff}}\). Therefore, the differential capacitance can be expressed as:

\[C_{\text{diff}} = \frac{dC}{dV} = q A N(W)_{\text{eff}} \frac{dW}{dV}.\]

Using the equation for the parallel plate capacitor (see above) and differentiating it with respect to the bias voltage, one can derive the following expression for the effective doping density:

\[N(W)_{\text{eff}} = \frac{2}{q \epsilon_{0} \epsilon_{Si} A^2 \frac{d}{dV}(\frac{1}{C^2})}.\]

1. Use the formula to calculate doping profile effectively at each bias voltage of the BPW34 diode. Use this along with the depletion width at each bias voltage, to create a plot of doping concentration vs depletion depth.

2. Where is the minimum of the doping profile located and how wide is the ‘I’ intrinsic layerm approximately? What is the the minimum doping density and how does this value compare with the intrinsic doping density of silicon?